當有數值放置於外部SRAM時,程式啟動時若尚未設置SRAM這時將會發生錯誤
通常這時需在進入程式前增加Startup Code,在進入程式前設定好SRAM周邊參數
檔案"stm32f10x_vector.s"
決定是否開啟SRAM設定
; If you need to use external SRAM mounted on STM3210E-EVAL board as data memory,
; change the following define value to '1' (or choose ENABLE in Configuration Wizard window)
;// <o> External SRAM Configuration <0=> DISABLE <1=> ENABLE
DATA_IN_ExtSRAM EQU 1
; change the following define value to '1' (or choose ENABLE in Configuration Wizard window)
;// <o> External SRAM Configuration <0=> DISABLE <1=> ENABLE
DATA_IN_ExtSRAM EQU 1
......
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler
IF DATA_IN_ExtSRAM == 1
; FSMC Bank1 NOR/SRAM1 is used for the STM3210E-EVAL, if another Bank is
; required, then adjust the Register Addresses
; Enable FSMC clock
LDR R0,= 0x00000114
LDR R1,= 0x40021014
STR R0,[R1]
; Enable GPIOD, GPIOE, GPIOF and GPIOG clocks
LDR R0,= 0x000001E0
LDR R1,= 0x40021018
STR R0,[R1]
; SRAM Data lines, NOE and NWE configuration
; SRAM Address lines configuration
; NOE and NWE configuration
; NE1 configuration
; NBL0, NBL1 configuration
LDR R0,= 0xB4BB44BB
LDR R1,= 0x40011400
STR R0,[R1]
LDR R0,= 0xBBBBBBBB
LDR R1,= 0x40011404
STR R0,[R1]
LDR R0,= 0xB44444BB
LDR R1,= 0x40011800
STR R0,[R1]
LDR R0,= 0xBBBBBBBB
LDR R1,= 0x40011804
STR R0,[R1]
LDR R0,= 0x44BBBBBB
LDR R1,= 0x40011C00
STR R0,[R1]
LDR R0,= 0xBBBB4444
LDR R1,= 0x40011C04
STR R0,[R1]
LDR R0,= 0x44BBBBBB
LDR R1,= 0x40012000
STR R0,[R1]
; FSMC Configuration
; Enable FSMC Bank1_SRAM Bank
LDR R0,= 0x00001011
LDR R1,= 0xA0000000
STR R0,[R1]
LDR R0,= 0x00000200
LDR R1,= 0xA0000004
STR R0,[R1]
ENDIF
IMPORT __main
LDR R0, =__main
BX R0
ENDP
ALIGN
Reset_Handler PROC
EXPORT Reset_Handler
IF DATA_IN_ExtSRAM == 1
; FSMC Bank1 NOR/SRAM1 is used for the STM3210E-EVAL, if another Bank is
; required, then adjust the Register Addresses
; Enable FSMC clock
LDR R0,= 0x00000114
LDR R1,= 0x40021014
STR R0,[R1]
; Enable GPIOD, GPIOE, GPIOF and GPIOG clocks
LDR R0,= 0x000001E0
LDR R1,= 0x40021018
STR R0,[R1]
; SRAM Data lines, NOE and NWE configuration
; SRAM Address lines configuration
; NOE and NWE configuration
; NE1 configuration
; NBL0, NBL1 configuration
LDR R0,= 0xB4BB44BB
LDR R1,= 0x40011400
STR R0,[R1]
LDR R0,= 0xBBBBBBBB
LDR R1,= 0x40011404
STR R0,[R1]
LDR R0,= 0xB44444BB
LDR R1,= 0x40011800
STR R0,[R1]
LDR R0,= 0xBBBBBBBB
LDR R1,= 0x40011804
STR R0,[R1]
LDR R0,= 0x44BBBBBB
LDR R1,= 0x40011C00
STR R0,[R1]
LDR R0,= 0xBBBB4444
LDR R1,= 0x40011C04
STR R0,[R1]
LDR R0,= 0x44BBBBBB
LDR R1,= 0x40012000
STR R0,[R1]
; FSMC Configuration
; Enable FSMC Bank1_SRAM Bank
LDR R0,= 0x00001011
LDR R1,= 0xA0000000
STR R0,[R1]
LDR R0,= 0x00000200
LDR R1,= 0xA0000004
STR R0,[R1]
ENDIF
IMPORT __main
LDR R0, =__main
BX R0
ENDP
ALIGN
在STM32中SRAM的控制器都屬於Bank1
不同的SRAM記憶體區塊對應到不同的SRAM_NE腳,需視SRAM所對應記憶體區塊去設定NE腳的GPIO configuration與SRAM_Bank的FSMC Configuration
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